A programmable logic array (PLA) is a compact way of implementing combinational logic functions (such as AND or OR logic) that involves a matrix of column and row lines in an input AND (or other logic function) plane and a matrix of row and column lines in an output OR (or other logic function) plane with the rows between the two planes appropriately coupled together. The AND plane generates specific logic combinations of the inputs and their complements. The outputs of the AND plane leave at right angles to its inputs and run horizontally to the inputs of the OR plane. The outputs of the OR plane then run vertically and may be stored in an output register. Various types of logic may be employed in each plane, other than AND or OR logic. In cases where it is necessary to know the outcome of the current data processing step before proceeding with the next step, some of the outputs are fed back as inputs. When outputs are fed back as feedback, such a sequential machine is known as a finite-state machine.
Complex synchronous sequential finite-state machines implemented on MOS integrated circuits are usually designed with programmable logic arrays, as this allows a modular and correctable design. A two clock phase logic system that evaluates once per clock cycle can be designed using a static NOR/NOR or AND/NOR programmable logic array. In this case the feedback lines are typically activated once per clock cycle through associated state variable latches that have two complementary outputs that form inputs to the NOR or AND plane. The inputs maybe applied continuously and are evaluated throughout the cycle except for the time necessary to set up the state variable latches. However, such systems can become unnecessarily complex in CMOS for static logic. Dynamic or clocked logic allows for creation of larger logic gates than may be employed in static logic. Complexity can be reduced by using a dynamic precharge/discharge PLA structure. However, such dynamic systems consume power even if the input signals remain the same.
PLAs are a convenient way to implement a specific type of communications protocol. For example, a PLA may be employed to implement aspects of a token ring or Ethernet network communications protocol for computers. Such aspects may be, for example, but not limited to, performing flaming functions; exemplary flaming functions might be delimiting flames, CRC generation and checking, and data serialization and deserialization.
Although communications protocols may be different, they often have a need for similar functions or functionality, and because of this may have some common input signals and/or output signals. One example of such similar functionality is performance of common flaming functions, as described earlier herein. It is possible to design and construct hardware that is capable of implementing one or more communications protocols that employs the same portion of the hardware for a given function or functionality, regardless of the protocol employed. This need to use one portion of the hardware to perform a given function, regardless of the protocol, may be caused by the desire to minimize chip size or the desire to use known working circuit designs to minimize design time. However, combining the PLAs of these known circuits into one PLA may not be possible for either size (too big) or operating (too slow) reasons. Thus, for such hardware there is a need for PLAs capable of implementing various types of communications protocols for both static and dynamic logic.
These and other disadvantages of the prior art are overcome by the present invention, however, and multiple, selectable PLAs having shared inputs and outputs are provided.